Test Generation for Asynchronous Sequential Digital Circuits

The dissertation thesis is aimed at test generation for asynchronous sequential digital circuits, contributes to their timeand cost-effective testing, and indirectly supports their wider application, which improves the performance, the power consumption and the electromagnetic emission of future digital circuits. The main scientific contribution is design of the new test generator (optimized for test length and area overhead) for wide spectrum of asynchronous sequential digital circuits. The contributions are identification of unacceptable signal transitions before test generation, reduced number of generated test patterns for combinational representation, effective state justification on the gate level, fast (optimized for test length) sequential fault propagation to outputs and effective fault simulation. Experimental results confirmed the generation of optimal tests with good fault coverage and without application of any method for increasing the testability. The developed methods can be used with wider spectrum of circuits than other recently developed test generators, and at the same time their effectiveness ensures fast test generation.